New JRC has launched "Analog Master Slice Shuttle Service"

August 9, 2012

Offering the original analog semi-customized IC/LSI developing easily and in a short period.

Tokyo Japan, August 9, 2012 – New Japan Radio Co., Ltd. (New JRC) has launched "Analog Master Slice Shuttle Service" which offers a collaborative use of the Analog Master Slice Service" to many different customers.

New JRC has delivered "Analog Master Slice Service" which can develop an analog ASIC for a short period.

The new service is a system making several kinds of IC chips, ordering from different customers, together on a same semiconductor wafer. Sharing the wafer with many different customers makes them easier to develop analog ICs than using the existing services.

There are many initially divided blocks (10 blocks or 30 blocks) in the wafer for different chips, and the customer can apply the service by one block. We hope our customers will enjoy their analog semi-customized IC/LSI developing easily and in a short period with our new service, and we will expand the base for analog circuit integration.

We provides various supports for analog IC developing and manufacturing, such as "Analog Master Slice Service", Shuttle Service" and "Foundry Service" to our customers. These services can allow our customers to enjoy their analog IC developing.


Schedule for Implementing

We will provide the service with a period fixed and invite customers.

1st : November, 2012 / 2nd : April, 2013 and we will provide the service twice more.

When the number of orders from customers does not meet our standards, the shuttle service may be canceled.

shared wafer

image of blocks

¥500,000 / one block
¥260,000 / additional one block

Block means each master slice chip assigned
  in the same wafer.

Approximate delivery

Sample shipping : 7 weeks after from the mask layout data receipt

[About Analog Master Slice]

The Analog Master Slice is the service which offers the original analog semi-customized IC/LSI for customers. The wafers which are prefabricated transistors, resistors, capacitors and other devices are prepared, then creation of the original IC/LSI is accomplished by adding the glass mask of wiring layers to be customized as desired. The cost and lead-time can be reduced since the common master slice is utilized. The lead-time for ES (engineering samples) is usually 4 weeks after the layout design is completed.

Standard customized IC/LSI usually takes at least 24 weeks.