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Thermal Resistance

INTRODUCTION

Generally, the life of a device would decrease to half, and the failure rate would double whenever Junction Temperature, Tj, goes up by 10°C. Moreover, when Tj exceeds 175°C, a device has the possibility of breaking.Therefore, it is necessary to keep Tj in the proper temperature range, which is the lower the better, and a heat design should be done under the condition of the range of 80-100℃.In fact, it is difficult for IC packages that handle high power to keep Tj in this range. Therefore, it is common to make Tj the 80% of a maximum permissible temperature.A value of a thermal resistance is dependent on a chip, a layout of a leadframe, a board, and so forth. It means even if sizes of the IC packages are the same and layouts of leadframes are different, thermal resistances are not the same.

DEFINITIONS

The thermal resistance of a IC package is calculated by the difference between Tj and the ambient Temperature, Ta, under the condition that the IC package dissipates electric power of 1W. Here are three expressions of the thermal resistance, and each term of expressions are defined in Table1 and Fig.1.

Thermal resistances
Thermal resistancesFig.1 Thermal resistances of a IC package
Table1 Definitions
Item Definitions
θja thermal resistance between Tj and Ta
ψjt thermal resistance between Tj and Tc1
θjc thermal resistance between Tj and Tc2
θca thermal resistance between Tc and Ta
Tj junction temperature
Ta ambient temperature
Tc1 temperature of the top surface of IC package
Tc2 temperature of the bottom surface of IC package
Pd maximum permissible power
Estimation of Tj when ψjt is known

Tj can be estimated by following order

  1. Power, P, is calculated by operating current and voltage.
  2. Tc1 is measured by using a thermometer like a radiation thermometer and thermocouples.
  3. Tj is calculated by Tc1, and ψjt which is shown in Table 3.
Tj=ψjt×P + Tc1

Note) θja and ψjt in Table 3 are measured values based on JEDEC with no wind.Each value is dependent on a chip, a layout of a leadframe, a board, and so forth.

Measurement of Thermal Resistance

The measurement of thermal resistance is based on JEDEC.

[Test board]

The outline of the measurement board is shown in Fig.2, which is based on JEDEC.

Measurement boardFig.2 Measurement board

Note)

  • Board material : FR-4
  • Board dimension:
    • ( 2-layer board ) 114.3x76.2mm,Thickness 1.57mm
    • ( 4-layer board with Cu foil 1,2 ) 114.3x76.2mm,Thickness 1.6mm
  • Cu foil dimension : 74.2x74.2mm (Thickness 35µm) are applied to 4-layer board, as Cu foil 1, 2.
[Chip for measurement of Thermal Resistance]

A chip is composed of elements of a resistance and a diode. The resistance is used for heating, and the diode is for a sensor of temperature. We have three kinds of size, because thermal resistance is dependent on a chip size.

Image of the chipFig.3 Image of the chip
[Measurement of K factor]

Tj cannot be measured directly. However, by a character of a forward voltage, V F of a diode is dependent on temperature. Therefore, Tj is known during a measurement by measuring VF.However, dependency of diode which called K-factor, K, should be measured first.

K-factor
[JEDEC chamber]
  • JEDEC chamber with no wind condition (still air) is adopted.The ambient temperature is measured with thermocouples at the position that is located 25.4mm below the center of the IC package.
  • JEDEC chamberFig.4 JEDEC chamber
[Measurement circuit] Measurement circuitFig.5 Measurement circuit
[Measurement procedure]
  1. VF0 is measured by giving the diode with a current (1mA), IM, at the ambient temperature.
  2. A Voltage, VH, is given to the resistance in the chip until temperature at upper surface of the IC package, which is measured with a radiation thermometer, is saturated. After confirming the saturation, IH is read.
  3. VFSS is measured by giving the diode with a current, IM.
Timing of measurementFig.6 Timing of measurement

Note) VH is measured at three points, the voltage of Tstg-max, Vstg-max, and lower and higher than Vstg-max.

[Calculation]

θja an ψjt are calculated from the following Table 2.

Table 2 Thermal resistance calculationThermal resistance calculation

[The Permissible Regions of Dissipated Power]

Pd is the maximum permissible power at Ta=25°C.Pd is dependent on the ambient temperture, which is shown in Fig.7.

Ambient temperatureFig.7 The maximum permissible power
Thermal Resistance of each package

There are typical measured value based on JEDEC with no wind. Each value is dependent on a chip, a layout of a leadframe, a board, and so forth.

Table 3 Thermal resistance of each package
PKG 2 layer board 4 layer board
Tj:125°C Tj:150°C Tj:125°C Tj:150°C
θja ψjt Pd@Ta=25°C θja ψjt Pd@Ta=25°C
(°C/W) (°C/W) mW (°C/W) (°C/W) mW
DMP82354742553017540570710
DMP141954751064015040665830
DMP161954751064015040665830
DMP2015037665830120338301040
SOP8 JEDEC(EMP8)18034555690125298001000
SOP16 JEDEC(EMP16-E2)110219051135701814251785
SOP816526605755110239051135
SOP14125218001000801712501560
SOP22120188301040851411751470
SOP2815537645805125338001000
SOP40-K113537740925105339501190
SSOP82704237046021036475595
SSOP8-A32153646558015515645805
SSOP102704237046021036475595
SSOP142253844055518033555690
SSOP162103547559516026625780
SSOP201853454067514026710890
SSOP20-B22003450062515026665830
SSOP20-C31301376596085911751470
SSOP32110209051135701414251785
SSOP44110209051135701414251785
TSSOP54-N110510950119075913301665
HSOP82)16028625780501220002500
HTSSOP24-P12)11514865108545722202775
MSOP8(TVSP8)2152746558016023625780
MSOP10(TVSP10)2152746558016023625780
MSOP8(VSP8)2103347559515525645805
MSOP10(VSP10)2103347559515525645805
SC-88A3558928035026073380480
SC-82AB3658927034025572390490
SOT-23-52607038048019560510640
SOT-23-62457040551017560570710
SOT-89-31)2)2006750062513065765960
QFP32-J2115178651085901511101385
QFP44-A1951710501315751513301665
QFP48-P1651715351920501520002500
LQFP48-R37591330166545522202775
LQFP52-H2851111751470651115351920
QFP56-A1105179501190801512501560
QFP64-H1701714251785501520002500
LQFP64-H26561535192050520002500
QFP100-U15551815227045522202775
TO-252-31)2)105179501190401225003125
PLCC2855101815227035728553570
EPFFP6-A22)3705927033522053450565
EPFFP10-C42)2956433542016055625780
PCSP12-C32404041552014033710890
PCSP20-CC2254044055514033710890
PCSP20-E32254044055513033765960
PCSP24-ED20540485605115268651085
PCSP32-F722524440555115178651085
PCSP32-G32)20524485605115178651085
PCSP32-GD2)20524485605115178651085
EPCSP32-L22)21029475595951610501315
DFN6-J1 (SON6-J1)3458828536026069380480
DFN4-F1 (ESON4-F1)2)30052330415110279051135
DFN6-H1 (ESON6-H1)2)28042355445110269051135
DFN8-U1 (ESON8-U1)2)28043355440110269051135
DFN8-V1 (ESON8-V1)2)2151646558070814251785
DFN8-W2 (ESON8-W2)2)1952151064060816652080
QFN24-T1/T215022665830751513301665
EQFN12-E22)28552350435105279501190
EQFN12-E42)28552350435105279501190
EQFN14-D72)29553335420952610501315
EQFN16-G22)255433904901002610001250
EQFN12-JE2)21522465580801012501560
EQFN16-JE2)18021555690701114251785
EQFN18-E72)22033450565902211101385
EQFN26-HH2)1601562578060716652080
EQFN24-LK2)1451368586065815351920
Notes
1) Thermal resistance values (θja,ψjt) are measured with the 2-layer board having 100mm2 copper foil, which is based on JEDEC.
2) Thermal resistance values (θja,ψjt) are measured with the 4-layer board having thermal via holes, which is also based on JEDEC.
Thermal Resistance depending on area of Cu foil

There are typical values by mounting on five kinds of boards, "PAT.1" through "PAT.5", shown in Table 4 and Table 5.Those are 2-layer boards based on JEDEC. However, they do not have any thermal via holes.

Thermal Resistance depending on area of Cu foilFig.8 Thermal Resistance depending on area of Cu foil Image of Cu foilTable 4 Image of Cu foil
teble TO-252 SOT-89 SOT-23-5
SOT-23-6
PAT.1 PAT PAT PAT
PAT.2 PAT PAT PAT
PAT.3 PAT PAT PAT
PAT.4 PAT PAT PAT
PAT.5 PAT PAT -
Table 5 Image of Cu foil
PAT SC-88A
SC-82AB
PAT.1 PAT
PAT.2 PAT
PAT.3 PAT
PAT.4 PAT
Table 6 Area of Cu foil
teble TO-252 SOT-89 SOT-23-5
SOT-23-6
SC-88A
SC-82AB
PAT.1 100mm2
PAT.2 225mm2
PAT.3 400mm2
PAT.4 600mm2 1600mm2
PAT.5 1225mm2 -